3D Circuits and Systems Group

3D FPGA PROJECT

FPGAs provide a flexible computing platform for system designers. This flexibility in the form of programmable switches and wiring grids to communicate among logic blocks leads the interconnect to contribute a high percentage of the power, delay, and area. This interconnect overhead accounts for 80% or more of power usage and 60% or more of delay and over 75% of the area in deep submicron processes.

3D Routing Switch There are a number of performance improvements that can be made by using 3-D integration, without drastically changing the FPGA topology. The most direct translation of FPGA architecture to a 3-D technology is by arranging the programmable function units (PFUs) in a 3-D mesh, as opposed to the 2-D mesh employed in conventional FPGAs. The routing switchboxes in 2-D FPGAs would be replaced by 3-D switchboxes that connect horizontal and vertical tracks with z-axis tracks to other wafers. In a 3-D mesh, each mesh node is adjacent to six neighbors versus four neighbors in a 2-D mesh; thus, a greater routing density is available in 3-D FPGAs than in 2-D FPGAs. As a result, PFU utilization in FPGAs may be improved. Alternatively, fewer programmable routing tracks are required by the 3-D architecture, resulting in a reduction by 45% to 60% of interconnect delays and power consumption, depending on the number of wafers used.

Increasingly, FPGAs are seen that employ more varied computational fabrics. Memories, special purpose units such as ALUs, and even whole processors are embedded within the PFU mesh. The inclusion of these components increases the average distance between any two PFUs, thus increasing delays and power consumption. Additionally, die size constraints limit the amount of functionality that can be incorporated into a single FPGA. By partitioning PFUs, programmable routing, memories, and processors onto separate wafers, it may be possible to maintain a dense PFU array while adding the required extra functionality. Also, memories such as DRAM can be integrated using a suitable process for their specific wafers. Finally, by using multiple dice of maximum size, linear increases in logic capacity can be achieved.

3D Place & Route and 3D Magic

PR3D is a placement and routing tool for standard cell design in 3D.
[ For more information and to download, follow this link ]

3D-Magic is a comprehensive layout methodology for 3D circuit layout editing and extraction with Magic, a widely used layout editor in academia.
[ For more information and to download, follow this link ]


	3D FPGA PROJECT
3DCSG Home People Publications Links Downloads Contact Us DICS Home MTL Home MIT Home	FPGAs provide a flexible computing platform for system designers. This flexibility in the form of programmable switches and wiring grids to communicate among logic blocks leads the interconnect to contribute a high percentage of the power, delay, and area. This interconnect overhead accounts for 80% or more of power usage and 60% or more of delay and over 75% of the area in deep submicron processes. There are a number of performance improvements that can be made by using 3-D integration, without drastically changing the FPGA topology. The most direct translation of FPGA architecture to a 3-D technology is by arranging the programmable function units (PFUs) in a 3-D mesh, as opposed to the 2-D mesh employed in conventional FPGAs. The routing switchboxes in 2-D FPGAs would be replaced by 3-D switchboxes that connect horizontal and vertical tracks with z-axis tracks to other wafers. In a 3-D mesh, each mesh node is adjacent to six neighbors versus four neighbors in a 2-D mesh; thus, a greater routing density is available in 3-D FPGAs than in 2-D FPGAs. As a result, PFU utilization in FPGAs may be improved. Alternatively, fewer programmable routing tracks are required by the 3-D architecture, resulting in a reduction by 45% to 60% of interconnect delays and power consumption, depending on the number of wafers used. Increasingly, FPGAs are seen that employ more varied computational fabrics. Memories, special purpose units such as ALUs, and even whole processors are embedded within the PFU mesh. The inclusion of these components increases the average distance between any two PFUs, thus increasing delays and power consumption. Additionally, die size constraints limit the amount of functionality that can be incorporated into a single FPGA. By partitioning PFUs, programmable routing, memories, and processors onto separate wafers, it may be possible to maintain a dense PFU array while adding the required extra functionality. Also, memories such as DRAM can be integrated using a suitable process for their specific wafers. Finally, by using multiple dice of maximum size, linear increases in logic capacity can be achieved. 3D Place & Route and 3D Magic PR3D is a placement and routing tool for standard cell design in 3D. [ For more information and to download, follow this link ] 3D-Magic is a comprehensive layout methodology for 3D circuit layout editing and extraction with Magic, a widely used layout editor in academia. [ For more information and to download, follow this link ] Sponsors DARPA Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Defense Advanced Research Projects Agency. MARCO Interconnect Focus Center

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3D Place & Route and 3D Magic

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