A 19pJ/pulse UWB Transmitter with Dual Capacitively-Coupled Digital Power Amplifiers
Patrick Mercier and Denis Daly
April 2007
A pulsed ultra-wideband transmitter operating in the 3-to-5GHz band is designed in 90nm CMOS. The all-digital architecture generates pulses by capacitively combining two paths which have in-phase RF signals, yet have counter-phase common-mode components that are canceled. This technique results in FCC-compliant pulse generation without requiring the use of any off-chip filters. The transmitter operates at a maximum data rate of 15.6Mbps, requires a core area of 0.07mm2, and achieves an energy efficiency of 19pJ/pulse. |
A Switched Capacitor DC-DC Converter for ultra-low-power applications
Yogesh Ramadass
November 2006
A switched capacitor DC-DC converter that could deliver scalable output voltages was designed in National Semiconductor's 0.18um CMOS process. The converter was able to deliver load voltages from 0.3V - 1.1V and was powered by a 1.2V battery. It employs on-chip charge transfer capacitors and reduces the loss due to bottom-plate parasitics by employing a method known as divide-by-3 switching. |
A 6-bit, 0.2V to 0.9V Highly Digital Flash ADC with Comparator Redundancy
Denis Daly
October 2006
A 6-bit highly digital flash ADC is implemented in a 0.18um CMOS process. The ADC operates in the subthreshold regime down to 200mV and employs comparator redundancy to improve linearity. Common-mode rejection is implemented digitally via an IIR filter. The ADC's minimum FOM is at a supply of 0.4V, where it achieves a FOM of 125fJ/conversion-step and a ENOB of 5.05 at 400kSPS. |
CMOS interface to CNT sensor arrays
Taeg Sang Cho
October 2006
The interface chip attains a large dynamic range using and ADC and DAC of lower dynamic range and an automatic control. The sensor interface chip is designed in a 0.18um CMOS process and consumes, at maximum, 32 uW at 1.83 kS/s conversion rate. The designed interface achieves 1.34% measurement accuracy over 10 kOhm - 9 MOhm dynamic range. The power consumption of the chip can be linearly scaled using duty-cycling. |
A 256kb 65nm 8T Sub-Threshold SRAM Employing Sense-Amplifier Redundancy
Naveen Verma
June 2006
An 8T SRAM achieves full read and write functionality at 350mV. The read-buffered bit-cell eliminates the read static noise margin limitation; peripheral control of the read-buffer eliminates sub-Vt bit-line leakage from unaccessed cells; peripheral control of the bit-cell supply voltage ensures write-abilty in the presence of variation; and the technique of sense-amplifier redundancy improves the area-offset tradeoff in the sensing network by over a factor of 5. |
A 400-mV UWB Baseband Processor
Vivenne Sze
May 2006
The baseband processor performs acquisition and demodulation of an UWB packet with a throughput of 500-MS/s for a data-rate of 100-Mb/s. It operates at an ultra-low supply voltage of 400-mV to achieve 20 pJ/bit, and utilizes a highly parallelized architecture to meet throughput constraints. It was fabricated in a standard-VT 90-nm CMOS process. |
A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS
Fred S. Lee
May 2006
The IC is a non-coherent 0-to-16Mb/s UWB receiver using 3-to-5GHz subbanded PPM signaling implemented in a 90nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65V. Using duty-cycling, adjustable BPFs, and an energy-aware baseband, the receiver achieves 2.5nJ/b and 10^(-3) BER with -99dBm sensitivity at 100kb/s. |
A 3.1-5GHz All-Digital UWB Transmitter
David D. Wentzloff
May 2006
This chip demonstrates an all-digital technique for generating UWB pulses with a programmable width and a center frequency tunable to 3 channels in the 3.1-5GHz band without the use of an RF oscillator. A delay-based spectral scrambling technique is proposed and implemented in this chip that exploits the delay-line based digital architecture to scramble the output spectrum. The main advantage of this scrambling technique is a drastic reduction of the hardware required to implement it, relative to the more commonly used BPSK scrambling. The transmitter uses only digital blocks, including the final stage driving the 50Ohm UWB antenna, which is a digital pad driver. The circuit consumes a total of 43pJ/bit at a data rate of 16.7Mb/s, including all core, control, and I/O power. |
Minimum Energy Tracking Loop with Embedded DC-DC Converter
Yogesh Ramadass
February 2006
An energy minimization loop, with on-chip energy sensor circuitry, that can dynamically track the minimum energy operating voltage of a digital circuit with changing workload and operating conditions occupies 0.05mm2 in 65nm CMOS. The DC-DC converter that enables this minimum energy operation can deliver load voltages as low as 250mV and achieved an efficiency >80% while delivering load powers of the order of 1uW and higher from a 1.2V supply. |
UWB digital baseband for 100Mbps transceiver
Raul Blazquez
August 2005
This baseband achieves 100Mbps using UWB impulses of
500MHz bandwidth in the FCC compliant band, as part of a UWB system.
Due to its bandwidth, the multipath becomes relevant. This digital
baseband allows to assess the quality of the channel and exposes
several knobs to fine-tune the receiver, trading off number of
operations and power dissipation with quality of service. It includes
a MLSE and a RAKE receiver to compensate for multipath. It has been
implemented in 0.18um CMOS technology.
|
A 50Mb/s UWB Prototype Transceiver
Nathan Ackerman, Raul Blazquez, Kyle Gilpin, Brian Ginsburg, Fred Lee, Vivienne Sze, David Wentzloff
August 2005
This prototype transceiver is built using discrete components. It communicates in a 500MHz band centered at 5.355GHz using BPSK pulses with a pulse repetition frequency of 50MHz. The received signal is down-converted to I/Q baseband signals using off-the-shelf discrete components. The baseband signals are digitized by dual 8-bit Atmel ADCs. Synchronization and demodulation are implemented in a Xilinx Virtex II FPGA enabling real-time communication at 50Mb/s. The transceiver communicates with a PC over USB2.0. Real-time one-way transmission of a video stream over the air has been demonstrated at a 50Mb/s raw data rate using this transceiver. |
An Energy Efficient OOK Transceiver for Wireless Sensor Networks
Denis Daly
May 2005
A 1 Mbps 916.5 MHz OOK transceiver for wireless
sensor networks has been designed in a 0.18-µm CMOS process.
The RX has an envelope detection based architecture with a
highly scalable RF front end. The RX power consumption scales
from 0.5 mW to 2.6 mW, with an associated sensitivity of
-37 dBm to -65 dBm at a BER of 10-3. The TX consumes
3.8 mW to 9.1 mW with output power from -11.4 dBm to
-2.2 dBm. The RX achieves a startup time of 2.5 µs, allowing
for efficient duty cycling. |
Fine Grain Power Domains with Dual-VDD for a Field Programmable Gate Array
Frank Honore
April 2005
A Field Programmable Gate Array test chip using 0.18um CMOS contains reconfigurable power domains to optimize active power consumption. Each configurable logic block and routing channel can operate at a choice of 2 voltages to reduce power consumption where longer latencies can be tolerated. On average a 54% reduction in power is achieved. |
500-MS/s 5-bit ADC with Split Capacitor Array
Brian Ginsburg
March 2005
A 500-MS/s, 5-b analog-to-digital converter (ADC) is implemented in 65nm CMOS technology. The ADC has six time-interleaved successive approximation register (SAR) channels that consume 6 mW from a 1.2 V supply. The ADC is the first implementation of the split capacitor array, replacing the conventional binary-weighted capacitor array of a SAR converter. The new array is faster and lower power without any degradation in linearity. |
Sub-threshold SRAM
Ben Calhoun
March 2005
A 256kb sub-threshold SRAM operates below 400mV from 0 to 85°C and is implemented in 65nm CMOS technology. For the same 6 sigma static-noise margin, the sub-threshold SRAM at 0.4V achieves 2.25-times lower leakage power and 2.25-times lower active energy than its 6T counterpart at 0.6V. The SRAM uses a 10T bitcell to enable sub-threshold functionality. |
Ultra Low Power ADC For Wireless Micro-Sensors
Naveen Verma
October 2004
A rate scalable (0-200kS/s) and resolution scalable (8b or 12b) ADC is
implemented using the successive approximation architecture. At the highest
performance point (12b, 100kS/s) it consumes just 25µW, and the power decreases
linearly with reduced sampling rate. Efficient operation is obtained through
several techniques: Analog offset compensation in the latch improves the
comparator power-delay product; robust self timing eases the settling time
requirements; and switched-capacitor auto-zero reference generation maximizes
common-mode rejection. |
Low-power Digital Processor for Wireless Sensor Networks
Daniel Finchelstein
October 2004
This chip explores the design of a low-power digital processor
for wireless network sensor nodes, employing techniques such as
hardwired algorithms, lowered supply voltages, and subsystem clock
gating. |
Dual 500 MSample/s 5-bit ADC chip
Brian Ginsburg
September 2004
Two analog-to-digital converters are integrated on this 0.18µm
CMOS chip to provide Nyquist sampling of quadrature UWB signals
that have been down-converted to baseband. The ADCs use a six-way
time-interleaved successive approximation register topoogy
to achieve a total 15.6mW core power consumption from a 1.8V
digital and 1.2V analog; the resolution is scalable down to
1-bit for further power savings. |
 UWB 100Mb/s 3.1-10.6GHz Transceiver Chipset
Fred Lee, David Wentzloff, Brian Ginsburg
June 2004
This chip is the RF front-end for a 100Mb/s pulsed ultra-wideband
(UWB) transceiver that communicates in 14 channels spaced 528
MHz apart in the 3.1-10.6 GHz band. It features an FCC compliant
BPSK pulse-shaping transmitter, a direct-conversion receiver
with 802.11a notch filtering, and two cross-coupled quadrature
VCOs. The chip was fabricated in a 0.18µm SiGe BiCMOS process. |
 Differential and Single Ended Elliptical Antennas for 3.1-10.6
GHz Ultra Wideband Communication
Johnna Powell
December 2003
The primary design is an ultra thin, low profile differential
antenna with an incorporated ground plane for use with a UWB
IC receiver. The differential capability eases the design complexity
of the RF Front-End, and the incorporation of a ground plane
enables conformability with small electronic UWB devices. Two
single ended designs are also presented for use with a UWB
IC transmitter. Both designs result in excellent bandwidth,
efficiency, and nearly omnidirectional radiation patterns. |
 Subthreshold Programmable FIR Filter Chip
Ben Calhoun
December 2003
A suite of programmable FIR filters designed for operation
in the subthreshold region provides insight into sizing for
minimum energy operation.
|
 Ultra-Dynamic Voltage Scaling Test Chip
Ben Calhoun
August 2003
This 90nm test chip demonstrates ultra-dynamic voltage scaling
using local voltage dithering for a suite of 32-bit Kogge-Stone
adders. The adders function from VDD at 1.2V to below 200mV,
extending the range of energy-delay scalability. |
 A 180mV FFT Processor Using Subthreshold Circuit Techniques
Alice Wang
June 2003
Minimizing energy requires scaling supply voltages below device
thresholds. The fabricated 1024-pt fast Fourier Transform (FFT)
processor operates down to 180mV using a standard 0.18µm
CMOS logic process while using 155nJ/FFT at the optimal operating
point. |
 Substrate Noise Characterization
Nisha Checka and David Wentzloff
December 2002
Substrate noise is a major problem that plagues mixed-signal
circuits. Parasitic interactions from switching digital circuits
propagate via the shared substrate to sensitive analog circuits
adversely affecting performance. A chip was designed to characterize
substrate noise generated by digital circuits as well as to
study the effect of substrate noise on the performance of a
standard component of the RF front-end, the voltage controlled
oscillator (VCO). The chip was fabricated in a 0.18 µm
CMOS mixed-signal process. |
 UWB Receiver Front-End
Fred Lee and Puneet Newaskar
December 2002
This is the lab's first UWB-related chip, consisting of a
LNA, a FLASH time-interleaved ADC, and a self-biased PLL. This
chip was used to test functionality of the ADC and high-speed
analog blocks that are required in a UWB system. |
 Energy Scalable FFT Chip
Alice Wang
June 2002
The scalable FFT chip demonstrates energy-aware architectures.
An energy-aware architecture is used to scale gracefully between
energy and quality. The architecture has variable bit precision
logic (multipliers, adders, etc.), memories (RAM and ROM) and
a variable memory size, in order to compute 128-1024-pt FFT
lengths and between 8- and 16-bit precision FFT's. |
 Low-power Multi-Threshold CMOS (MTCMOS) FPGA Chip Utilizing
Fine-Grained Leakage Management
Ben Calhoun, Frank Honore
March 2002
This 0.13µm, dual VT test chip uses MTCMOS-style logic
to implement a low-power FPGA architecture. The FPGA circuits
reduce standby leakage by over 8X while holding their state.
Idle sub-blocks in the design automatically enter sleep mode
at a fine granularity, reducing active off-current by up to
several times. |
 µAMPS-1 Node
Nathan Ickes, Fred Lee and Piyada Phanaphat
February 2002
The µAMPS-1 microsensor node uses commercial, off-the-shelf
(COTS) components for rapid construction. A µAMPS-1 node
consists of a stack of three or four printed circuit boards.
The top board contains the radio, including the RF circuitry
and the FPGA used for digital coding and decoding. The second
board contains an Intel StrongARM processor and associated
RAM and flash ROM. Also on the processor board are an acoustic
sensor (microphone, amplifier, filter, and analog-to-digital
converter) and a collection of dc/dc power converters that
service the entire node. The optional third board in the stack
is an additional sensor module to replace the acoustic sensor
on the processor board. The µAMPS-1 node can be easily
adapted to different applications by designing an appropriate
sensor board. |
 6.5GHz CMOS Frequency Synthesizer with FSK Modulator
Seong Hwan Cho
May 2001
This chip will enable energy efficient communication for low
power wireless sensor networks. Fabricated in 0.25µm
BiCMOS process, the modular achieves 20µs start-up time with
2.5 Mbps data rate while consuming 22mW, where 18mW is consumed
in the VCO and 4mW is consumed in the PLL.
|
A 175mV Multiply-Accumulate Unit using an Adaptive Supply
Voltage and Body Bias (ASB) Architecture
James Kao and Masayuki Miyazaki
December 2000
These photos show the 16-bit MAC (top photo) evaluated by
the ASB control (bottom photo). The ASB selects the optimum
combination of F/Vdd/Vbb including forward substrate biases.
The MAC operates at the lowest Vdd of 175mV.
|
 Optical Clocking Chip
Shiou Lin Sam
December 1999
This test chip consists of an optical receiver and detector
designed to investigate the effects of variation and to characterize
area and power requirements of an optical interconnect system.
|
 Low Power Sensor DSP for Biomedical Applications
Rajeevan Amirtharajah
February 1999
This DSP chip is targeted toward low and medium throughput
sensor applications. It is a hybrid architecture consisting
of custom filtering units and a programmable microcontroller.
It has run a real-time acoustic heartbeat detection algorithm
successfully at a power consumption of 560 nW at 1.5 V. |
 Vibration-to-Electric MEMS Device
Jose Oscar Mur-Miranda
Mechanical vibrations are converted into electrical energy
by using a MEMS variable capacitor. The variable capacitor
consists of a 1.5cm-by-0.5cm silicon structure etched in a
wafer of 500µm thickness. |
 Domain Specific Reconfigurable Cryptographic Processor
James Goodman
January 1999
The DSRCP utilizes a dynamically-reconfigurable datapath to
implement a variety of public key cryptographic primitives
and algorithms including large integer arithmetic (8 - 1024),
both prime and binary Galois Field arithmetic (GF(2^8) - GF(2^1024),
and GF(p) for 2^8 < p < 2^1024), and Elliptic Curve arithmetic
over both integer and binary Galois fields. |
 Distributed 1.3 GHz System Clock Generation Chip
Vadim Gutnik
October 1998
16 Oscillators and 24 phase detectors form a distributed,
symmetric phase-locked loop that is guaranteed to lock with
the phases aligned, and generate a 1.3 GHz clock over the entire
3mm x 3 mm chip. Fabricated in a 0.35 micron TSMC process,
the chip consumed 130 mA and 3V. |
 Parallel Fine-Resolution Time Sampling Chip
Vadim Gutnik
October 1998
Proof-of-concept chip for fine-resolution, one-shot, digital
time-interval measurements. An array of arbiters samples two
input clocks and outputs binary measurement results. External
calibration of the mismatches between the arbiters allows the
outputs to be converted to a time measurement accurate to approximately
2ps. Fabricated in a 0.35 micron TSMC process. (A second array
introduces fixed RC delays between the arbiters and thus allows
larger dynamic-range measurements at the cost of lost precision.) |
 A Low Power Controller for a MEMS Based Energy Converter
Scott Meninger
October 1998
This chip consists of a low power digital control core and
optimized power switches which act in concert with a MEMS (micro-electromechanical
systems) variable capacitor to harvest ambient vibrational
energy for use by low power electronic loads. |
 DCT Core Processor
Thucydides (Duke) Xanthopoulos
October 1998
The DCT core processor computes the Discrete Cosine Transform
on 8x8 blocks of picture elements. It exploits signal correlation
and quantization for arithmetic activity minimization and low
power operation. The chip dissipates 4.3 mW at 1.5V, 14 MHz. |
 Low Power Video Encoder
Thomas Simon
October 1998
This wavelet based full motion video encoder performs scalable
compression on 30 frames/sec at 128x128 resolution. The encoder
dissipates 400-800 µW depending on the spatial and temporal
content in the video stream. |
 DC/DC Converter for Self-Powered Signal Processing
Rajeevan Amirtharajah
An ultra-low power DC/DC converter is implemented in this
chip to enable a load DSP to be powered from ambient mechanical
vibration. It uses performance feedback to implement low resolution
digital control. Its power consumption is 14 microwatts at
1V. |
 IDCT Core Processor
Thucydides (Duke) Xanthopoulos
The IDCT core processor computes the Inverse Discrete Cosine
Transform on 8x8 blocks of spectral coefficients. It features
a clock-gated pipeline that reduces the total system duty cycle
in the presence of zero valued spectral coefficients. The chip
dissipates 4.5 mW at 1.3V, 14 MHz. |
 QRG w/embedded DC-DC Converter
James Goodman
May 1997
Extension of the QRG to utilize an embedded switching DC-DC
converter. The DC-DC converter utilizes pulse-width modulation
to generate very high efficiency (90-95%) variable supply voltages.
The QRG and embedded converter are coupled via a performance
feedback control circuit that allows you to operate at the
minimum required supply voltage for a given application. |
 Variable Length Decoder
Seong Hwan Cho
March 1997
This chip is a low power variable length decoder for MPEG-2
system, fabricated in 0.6µm CMOS process. By exploiting
incoming signal statistics, the chip consumes 500µW, which
is more than an order magnitude lower power than existing architectures. |
 Quadratic Residue Generator (QRG)
James Goodman
August 1996
The QRG is utilized to generate high quality pseudo-random
data for use in stream ciphering systems. The QRG utilizes
a reconfigurable datapath to performs big-integer arithmetic
operations on operands ranging from 8 - 512 bits in size. The
QRG utilizes both conventional clock gating and self-timed
gating to minimize the switched capacitance. |
 DC-DC Converters With High Efficiency Over Wide Load Ranges
Joshua Bretz
This DC-DC converter introduces several novel circuits which
enables efficient operation at output powers from 100µW to
1W. Depending on the load current, the regulator automatically
switches between Pulse Frequency Modulation (PFM) and Pulse
Width Modulation (PWM), and automatically selects the optimum
size for the switching MOSFET. |
 A Reconfigurable Dual Output Low Power Digital PWM Power
Converter
Abram Dancy
This versatile power converter controller provides dual outputs
at a fixed switching frequency and can regulate either output
voltage or target system delay. Efficiency of > 90% has
been demonstrated for low output power levels (milliwatts). |
 Controller for a Variable Supply Voltage Power Supply
Vadmin Gutnik
A simple feedback loop determines the supply voltage and system
clock frequency needed to just satisfy a computation throughput
constraint. The power controller, and a counter to model DSP
take 0.4 square mm and 1mW. |
